1. Field of the Invention
This invention relates to electrolytic etching of metal layers and more particularly to removal of thin metal layers from semiconductor substrates and still more particularly to removal of overplate layers in the production of integrated circuits formed from low-k dielectric interconnects.
2. Brief Description of the Prior Art
The integrated circuits (ICs) that are the fundamental components in modern computers and similar electronic devices are continuously increasing in complexity and performance. Moore's Law, attributed to Intel Corp. cofounder Gordon Moore, predicts that every 18 to 24 months the performance of ICs doubles without a corresponding increase in their cost. This doubling of performance is directly related to the number of transistors that can be packaged into an IC or chip. For example, in 1971 there were ˜2000 transistors per chip. More recently, in 1993, the Intel Pentium contained 3.1 million transistors and in 2000 the Pentium 4 had 40 million transistors. The Moore trajectory is expected to be maintained for another 15 years. The trajectory will be maintained by increasing wafer size and reducing the size of the smallest features and interconnects from about 180 nm, which is the current state-of-the-art, down to about 35 nm or less. However, adoption of feature sizes less than about 250 nm has already necessitated the replacement of aluminum conductors with copper, and the transition to feature sizes less than about 100 nm will require replacing the silicon dioxide dielectric material with material having a lower dielectric constant, i.e., less than about 3, that is, so-called low-k materials.
ICs or chips include multiple layers of wiring connecting transistors and other circuit components. A simplified process sequence for fabricating the wiring in a single layer includes: 1) deposition of a dielectric layer using chemical vapor deposition (CVD), 2) patterning and etching metal wiring features in the dielectric layer, 3) metallizing these features using physical vapor deposition (PVD) followed by electroplating, and 4) removing the metal overplate and planarizing the wafer using chemical mechanical polishing (CMP). This simplified process sequence may be repeated up to 40 times, to add hierarchical wiring layers, for a single IC.
Chemical mechanical polishing (CMP) is a process for removing the conductive metal, e.g., copper, overplate in the preparation of a damascene conductor layer on a semiconductor substrate. The surface of the electroplated wafer is abraded using a pad and an abrasive slurry or the like to remove overplated metal and sometimes some of the dielectric layer, thereby isolating the damascene conductors in their trenches. The CMP step also assures a flat surface for applying the next layer of photoresist.
Although CMP is an effective method of planarizing a plated damascene conductor layer when the dielectric layer is made from a hard dielectric material, such as silicon dioxide, problems have arisen when CMP is used with the newer low-k dielectric materials. The low-k dielectrics are somewhat softer than silicon dioxide and possess less mechanical strength. Specifically, under the 3 pounds per square inch (psi) pad pressure typical of the CMP process, the resultant strain of the low-k material is approximately 30 times that of copper. Consequently, the low-k material is easily abraded, distorted, or torn by conventional CMP. This damage may lead to distorted or broken damascene interconnects, delamination between the copper and the dielectric material and/or imperfect planarization.
Accordingly, a need has continued to exist for a method of removing metal overplate from damascene interconnect layers and planarizing the layer that does not suffer from the problems of CMP.